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Impedance Mask-Based PDN Specifications for Memory Modules & PCBs

Larry D Smith  (Principal power integrity engineer, Micron)

Tim Hollis  (Fellow - Signaling R&D, Micron)

Location: Ballroom G

Date: Thursday, January 30

Time: 12:00pm - 12:45pm

Track: 10. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Until now, the DRAM industry has offered little guidance to Module and system PCB designers concerning the PDN requirements to supply DRAMs with clean power. This paper develops an impedance mask which highlights and specifies the properties that the board(s) must have to satisfy DRAM power consumption. The impedance mask comprises capacitive, resistive and inductive components. A compliance methodology is proposed to determine if a Module or PCB design complies with the impedance mask specification. Failure to meet the impedance mask renders the board at risk for excessive PDN noise, while greatly exceeding the impedance mask adds significant cost to the PDN.


DRAM system PCB and Module designers need guidance for PDN design. An impedance mask is used to insure the PDN is strong enough to support the DRAMs. Pass/fail compliance criteria is generated from DRAM properties. The impedance mask is scaled by the number of DRAMs for PCBs populated with multiple DRAMs.

Intended Audience

Basic knowledge of electrical engineering.

Presentation File