April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC Die


James Kuszewski  (Consulting Engineer, Northrop Grumman)

Ramzi Vincent  (Senior Principal Digital Engineer, Northrop Grumman)

William McCaffrey  (Digital Hardware Engineer, Northrop Grumman)

Albert Park  (Digital Engineering Manager, Northrop Grumman)

Benjamin Dannan  (Staff Digital Engineer, Northrop Grumman)


Shin Wu  (Staff Digital Engineer, Northrop Grumman)

Location: Ballroom F

Date: Wednesday, April 6

Time: 11:15 am - 12:00 pm

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 02. Chip I/O & Power Modeling

Format: Technical Session

Theme : Data Centers, High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. The traditional methods of evaluating power integrity for an ASIC die on a substrate are generally lacking sufficient accuracy. The key element for system-level Power Distribution Network (PDN) analysis is a chip die model, which requires specialized EDA tools to create. These Electronic Design Automation (EDA) solutions typically create chip models using either vector-based or vectorless dynamic current profiles. Vector-based chip model solutions are challenging to create and typically do not cover the complete ASIC die use cases. In addition, the benefits of models created for the die, substrate, and PCB have multiple possible configurations such as lumped, distributed, looped and partial. This paper provides a novel workflow on the benefits of using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN. Lastly, this paper provides an improved methodology to determine if the voltage ripple at the die bumps on a substrate is violating the defined specification of the ASIC, and shows a method of evaluating the PDN target impedance across a system.


Key Takeaways (50 words max):
1. Know what your target PDN impedance needs to be for your VRM, board, substrate and die.
2. A clear methodology on how to know if the voltage ripple at the die bumps on a substrate is within the defined specification of the ASIC.