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Billy Koo (Principal Eng'r, samsung foundry)
Location: Ballroom F
Date: Wednesday, January 29
Time: 8:00am - 8:45am
Track: 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 06. System Co-Design: Modeling, Simulation & Measurement Validation
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Emerging new applications such as HPC(high performance computing), AI, autonomous vehicles, and high-speed networking require extremely high memory bandwidth and low power efficiency. HBM2 and GDDR6 memory interface are suitable candidates for the trend that requires such an enormous memory bandwidth. GDDR6 as offering a 2x increase in per-pin bandwidth over GDDR5, while maintaining compatibility with the established GDDR5 ecosystem. HBM2E extends data rate from 2.4Gbps to 3.2Gbps result in higher data transfer
To ensure over 16Gbps GDDR6 platform, we utilize unique equalization capabilities that are challenging to model and simulate. Also various measured results will be shown as enabling reference for other GDDR6 platform designers. For 3.2Gbps low power HBM2E platform solution, all digital DLL for DQS-DQ centering and command bus training(CBT), auto DQS cleaning and READ/WRITE training will be introduced.