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Subin Kim (Ph.D Candidate, Korea Advanced Institute of Science and Technology)
Kyungjun Cho (Ph.D Candidate, Korea Advanced Institute of Science and Technology)
Shinyoung Park (Ph.D Candidate, Korea Advanced Institute of Science and Technology)
Hyunwook Park (Ph.D Candidate, Korea Advanced Institute of Science and Technology (KAIST))
Gapyeol Park (Ph.D Candidate, Korea Advanced Institute of Science and Technology)
Seungtaek Jeong (Ph.D Candidate, Korea Advanced Institute of Science and Technology)
Joungho Kim (Professor, Korea Advanced Institute of Science and Technology)
Location: Ballroom F
Date: Wednesday, January 29
Time: 2:00pm - 2:45pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
With development in high performance computing system, increasing operation frequency and lowering supply voltage make logic circuits and output drivers more vulnerable to power noise coupling. However, the conventional off-chip VRM is limited to efficiently supply a stable power due to its electrical long distance to chip. In this paper, we firstly proposed, designed and analyzed an integrated voltage regulator (IVR) on active interposer. With power noise suppression effect of the proposed IVR, it is verified that 512GB/s bandwidth and under 1.0V supply voltage operation of 3D artificial intelligence computing system based on next generation HBM can be achieved.
We firstly proposed, designed and analyzed an integrated voltage regulator (IVR) on active interposer. With power noise suppression effect of the proposed IVR, it is verified that 512GB/s bandwidth and under 1.0 V supply voltage operation of 3D AI computing system based on next generation HBM can be achieved.
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