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Interconnect Design Practice Beyond 56-Gbps PAM4 System

Greg Fu (SI Engineer, Cisco)

Sherman Chen (Senior SI engineer, Cisco)

Stephen Scearce (Manager, Hardware Engineer, Cisco)

Location: Ballroom E

Date: Wednesday, January 30

Time: 11:00am - 11:45am

Track: 08. Optimizing High-Speed Serial Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

When SERDES rate switched to higher rate like 56Gbps/112Gbps PAM4, the ignored second effects of the interconnect actually play an important role in the system performance. The work present interconnect design practice from both component and system level. Some effects are investigated in details: Skew impact on XT, skew compensation strategy on XT, asymmetric fanout pattern, XT through footprint antipad, impact of different impedance system on ILD. A set of design guide are summarized and have been implemented into the present system.

Takeaway

skew will not only make IL worse, but also XT.
skew compensation strategy need to be careful on XT.
Make differential pair really differential is very important.
Be careful for XT through antipad.
More practical evaluation metrics of ILD will be helpful.

Intended Audience

High speed designer

Presentation Files

SLIDES_08_InterconnectDesignPracticeBeyond56Gbps_Fu.pdf
PAPER_08_InterconnectDesignPracticeBeyond56Gbps_Fu.pdf