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Anna Wong (Senior Engineer Manager, Xilinx Inc)
Gordon Tsui (Senior Engineer, Xilinx Inc.)
Haixin Ke (Power and Signal Integrity Engineer, Xilinx)
Ajay Kumar Sharma (Senior Manager, Xilinx)
Yongzhen Chen (Signal Integrity Characterization engineer)
Alisa Scherer (Independent Contractor)
Location: Ballroom C
Date: Thursday, January 30
Time: 12:00pm - 12:45pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
As data rate increases and the clock period gets smaller, jitter becomes an increasingly critical component to the overall timing budget. It is necessary to understand jitter behavior and to model it accurately to meet the speed target. This paper will first describe and define period jitter and its main source on silicon die as power supply noise. Next, we will detail the factors that can influence jitter behavior in order to better understand and model it. These include victim clock frequency, clock path delay, and noise frequency etc. We will also present measurements to support our explanations.
Period jitter is becoming a critical component of the timing budget in an effort to meet higher speeds. We talk about the various factors that can influence jitter behavior caused by power supply noise (power supply induced jitter, PSIJ). We also support our explanations with measurements from Xilinx FPGA.