Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
Location: Ballroom F
Date: Thursday, January 30
Time: 2:50pm - 3:30pm
Track: 12. Applying Test & Measurement Methodology, 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC)
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Advanced equalization consisting of CTLE and DFE is needed for current and future generations of serial data standards to compensate for loss and maintain required bit error rate. The jitter decomposition methodology that emerged few decades ago was the first attempt to better understand the source of timing variations and effect on link performance. While such analysis after CTLE is straightforward, measuring jitter after DFE still is not fully understood or standardized. The paper will discuss models and practical measurement considerations for jitter measurements after DFE as well as implications for transmitter compliance testing in various standards.
Understand how jitter transforms and affects the receiver with decision feedback equalizer. Learn about different DFE implementations and behavioral models used in compliance testing.
Basic understanding of serial data link, transmitter and receiver equalization, CTLE and DFE operation is desirable.