April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA


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Learning Super-scale Microbump Pin Assignment Optimization for Real-world PCB Design with Graph Representation

Speakers:

Joonsang Park  (Graduate student (M.S), Korea Advanced Institute of Science and Technology, KAIST)

Joungho Kim  (Professor, KAIST)

Authors:

Minsu Kim  (Graduate student (M.S), Korea Advanced Institute of Science and Technology, KAIST)

Seonguk Choi  (Graduate Student (M.S), Korea Advanced Institute of Science and Technology, KAIST)

Jihun Kim  (Graduate student (M.S), Korea Advanced Institute of Science and Technology, KAIST)

Haeyoen Kim  (Graduate Student (M.S), Korea Advanced Institute of Science and Technology, KAIST)

Hyunwook Park  (Graduate Student (PhD), Korea Advanced Institute of Science and Technology, KAIST)

Seongguk Kim  (Graduate Student (PhD), Korea Advanced Institute of Science and Technology, KAIST)

Taein Shin  (Graduate Student (PhD), Korea Advanced Institute of Science and Technology, KAIST)

Location: Ballroom E

Date: Wednesday, April 6

Time: 11:15 am - 12:00 pm

Track: 14. Machine Learning for Microelectronics, Signaling & System Design, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Format: Technical Session

Theme : Autonomous, Data Centers

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

Recently, to meet the increasing demand of high bandwidth systems, the number of I/Os and interconnections for 2.5D/3D ICs is also growing. Accordingly the pin count of the ball grid array (BGA) is getting larger along with signal integrity issues. In this paper, we propose BGA-opt, a novel deep reinforcement learning (DRL)-based pin assignment method that represents ball grid array (BGA) packages on graphs for minimizing signal integrity degradation. The proposed method represents the pin arrangement of BGAs in graphs to formulate the pin assignment task to a variant of the maximum independent set (MIS). Then, a state-of-the-art DRL-based MIS solver was introduced to solve our task. Unlike previous methods of BGA optimization, the proposed graph representation of pins makes it possible to assign pins of any shape. Moreover, the significant scaling performance enables us to handle BGA with high pin count. We verify that the proposed DRL-based method with graph representation is effective by comparing it with conventional meta-heuristic methods including genetic algorithm.

Takeaway

We propose a deep reinforcement learning-based pin assignment optimization method with graph representation for large scale ball grid array (BGA) pins. The proposed method coined BGA-opt, can apply real world constraints by representing the BGA as a graph. It significantly outperforms meta-heuristic methods on an objective concerning signal integrity with much faster speed and excellent scaling performance.