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Kevin (Kai) Li (SI/PI Engineering Manager, Synopsys)
Priyank Shukla (Staff Applications Engineer, Synopsys)
Jianguo Zhou (Senior SI/PI Engineer, Synopsys)
Christian de Verteuil (Senior R&D Manager, Synopsys)
Location: Ballroom D
Date: Wednesday, January 29
Time: 11:00am - 11:45am
Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Optimizing High-Speed Serial Design
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
PCIe 5.0 poses a few design challenges for the PHY due to high data rate and channel loss target. In this paper, we will describe case studies that demonstrate efficient optimization of RX architectural designs in the areas of CTLE, DFE and CDR IQ adaptation, by exploring system simulation results with different interconnect channels and alternative design choices. Furthermore, we will highlight precise modelling and verification strategies of TX and RX front-end. Finally, model to silicon correlation results over PVT corners are demonstrated to prove the high-fidelity of PCIe 5.0 PHY models.
A high fidelity IBIS-AMI model can be used for PCIe5 PHY architectural design optimization.
We present our PCIe5 IBIS-AMI system simulations with different channels and design alternatives for efficient solution space optimization.
High fidelity IBIS-AMI model is achieved by accurate front-end modelling with on-die 4-port S-parameter and reliable silicon correlation