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Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Lightning Talk – Power Estimation Methodology for Wireless Chipsets

Pavan Kumar Holla (Senior Engineer, Qualcomm Technologies Inc)

Vivek Gopal (Staff Engineer, Qualcomm Technologies Inc)

Prakash Parikh (Principal Engineer/ Manager, Qualcomm Technologies Inc)

Location: Chiphead Theater

Date: Wednesday, January 29

Time: 3:30pm - 3:40pm

Track: Chiphead Theater, 02. Chip I/O & Power Modeling & Validation Solutions

Format: Lightning Talk

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

Lightning Talks are technical papers that were accepted as part of the DesignCon conference, but are being made available to all attendees as short sessions in the Chiphead Theater.

Paper description: Wireless lan chipsets are ubiquitous, from mobile phones to IOT devices. Power consumption in these battery operated devices is critical, with wireless technologies using about 20% of mobile battery power. We propose a methodology to estimate and optimize the power consumption of wireless lan systems. We outline critical power consumption scenarios in wlan systems, followed by a method for early power estimation. Our method also refines the power estimates once the netlist and software become available. Our methodology identifies opportunities for power reduction at various stages of design of a wireless chipset.

Takeaway

A systematic analysis of wireless lan from a power perspective, followed by a method to estimate power throughout the multiyear chip-design process. The method will cover early architectural evaluation using power artist, comparison of netlist and powerartist power estimates, and software optimization for power.