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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Ethan Koether (Power Integrity Engineer, Project Kuiper - Amazon)
Mario Rotigni (Lead EMC Engineer for Automotive Microcontroller and SoC Team, STMicroelectronics)
Istvan Novak (Power Integrity Engineer, Samtec)
Kristoffer Skytte (Senior Principal Application Engineer, Cadence)
Joseph Hartman (Principal Hardware Engineer, Oracle Corporation)
Shirin Farrahi (Principal Software Engineer, Cadence)
Sammy Hindi (Senior Principal Engineer, Ampere Computing)
John Phillips (Principal Application Engineer, Cadence)
Location: Ballroom H
Date: Wednesday, April 6
Time: 11:15 am - 12:00 pm
Track: 10. Power Integrity in Power Distribution Networks, 06. System Co-Design: Modeling, Simulation & Measurement Validation
Format: Technical Session
Theme : Data Centers
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
The interaction of plane resonances in multi-layer, multiple power-domain board designs is explored for both a production and a test board. We will examine how the parameters of the plane cavities impact noise coupling in consideration of both resonance frequency and Q-value. The effects will be examined in both frequency and time domains for a simple step response. Methods to reduce coupling will also be explored, including thin laminates.
Cavity resonance noise can propagate across multiple power domains. A key indicator to the risk is the Q of the cavity. Thin laminates can lower cavity Q.
For all audience levels.