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Location: Ballroom C
Date: Thursday, January 30
Time: 8:00am - 8:45am
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC)
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Shortcuts that were taken in the early development phases of a VPU product were found to be the cause of functional failures on the LPDDR4 bus. A case study is presented detailing the discovery and debug of the failures (they were found to be caused by SSN) and the steps taken to remediate these failures. To validate the fixes before production, a new SI/PI co-simulation methodology was developed to provide for full channel post-layout modeling. Measured data is provided to showcase the before/after fixes and to compare against simulation results to build confidence in the co-sim method
- Production quality case study of a poor package PDN manifesting as signaling failures
- Debug procedure to flesh out the rootcause of failure modes
- Ways to fix PDN poor design without largely impacting platform/program schedule
- SI/PI co-simulation for better eye margin prediction
- Simulation measurement correlation