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Alex Manukovsky (Technical Lead, SI/PI Team, Intel)
Yuriy Shlepnev (President and Founder, Simberian Inc.)
Zurab Khasidashvili (Senior Software Engineer, Intel)
Eli Zalianski (Electrical Validation Engineer, Intel)
Location: Ballroom F
Date: Wednesday, January 29
Time: 12:00pm - 12:45pm
Track: 14. Machine Learning for Microelectronics, Signaling & System Design, 06. System Co-Design: Modeling, Simulation & Measurement Validation
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
This paper describes a systematic approach for the design space exploration of 112Gb SerDes systems based on Channel Operating Margin (COM) simulation methodology, through the application of machine learning (ML) methods for advanced system analysis. First, the solution space is mapped, and multiple channel models are generated with EM simulator corresponding to the cases of interest. Then an investigation of system level performance, covering various channel topologies, is conducted using COM methodology. Finally, we perform an ML-based design exploration, identifying the root-cause of the failures in the design, and an insight on how to optimize the design is provided.
A systematic approach is required to address SerDes design solution space coverage for multiple equalization mechanisms and various channel configurations affecting the system performance. We demonstrate a practical application of ML based methods to identify the parameters and combinations thereof having the greatest effect on the design/system output, account for failure to meet the specs/standards, and provide an insight on how to optimize the design. This method is implemented on a 112Gb system case study
Basic S parameters knowledge,
Basic understanding of SerDes equalization mechanism: FFE, DFE, CTLE.
Basic understanding of COM and ERL metrics