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Machine Learning Applications for Simulation & Modeling of 56 & 112-Gb SerDes Systems

Adam J Norman (Engineer, Intel)

Roee Bloch (Hi Speed Engineer, Intel)

Alex Manukovsky (Technical Lead, SI/PI Team, Intel)

Yaron Juniman (Senior SI Engineer, Intel)

Zurab Khasidashvili (Senior Software Engineer, Intel)

Location: Ballroom B

Date: Thursday, January 31

Time: 9:00am - 9:45am

Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 02. Chip I/O & Functional Block Modeling & Validation Solutions

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

This work describes a method for high-precision SerDes system modeling, and a predictive compliance simulation of high speed serial interfaces applicable for 25/56/112 Gb rates PAM4 and NRZ signaling. This method provides an accurate parametric macromodel using Machine Learning (ML) methods applied on measurement data, taking into account the controlled and uncontrolled variation in manufacturing tolerances as well as variation by design. The measurement based macromodel describes the system response with high precision for each case of interest, thus enabling an accurate compliance prediction. The method allows a high volume of simulation without requiring a high computational power.


Modeling 112 Gb SerDes systems, using Machine Learning (ML) methods applied on a measurement data. Learn how to take into account the controlled and uncontrolled variation in manufacturing tolerances as well as variation by design. Learn how to simulate 25/56/112 Gb PAM4 and NRZ systems accurately predicting compliance metrics.

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