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Maximizing DDR5 Eye-Opening by Identifying Buffer Settings Using Optimization Algorithms

Nitin Bhagwath  (Product Architect, Mentor Graphics)

Daniel De Araujo  (Principal Product Architect, Mentor Graphics)

Jayaprakash Balachandran  (Technical Lead, Cisco)

Baekkyu Choi  (Principal Engineer, Micron)

Location: Ballroom F

Date: Thursday, January 30

Time: 12:00pm - 12:45pm

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Due to longer trace lengths relative to faster operations, DDR5 DRAMs support 4 taps of DFE. Controllers will likely also support Tx and Rx equalizers. Furthermore, address signals now also support ODT within the DRAMs.

Which combination of settings will yield the optimal eye-opening in a given design? What is an efficient methodology to find such an optimal eye-opening? Using brute-force methods to analyze all combinations is computationally prohibitive, especially when designing 16+ such channels in a system.

In this paper, we discuss Optimization methods which may be used to find the largest DDR5 eye-opening in an efficient manner.


DDR5 includes 4-taps of DFE on the DRAM, and likely equalization on the Controller. In combination with multiple ODT settings, the number of valid combinations to select an optimal setting from is extremely large.

The paper discusses Optimization techniques to find optimal solutions in an efficient manner.

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