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Memory Options for High Performance Applications

Sreeja Menon (Principal Engineer IP Cores Architecture, Rambus)

Frank Ferro (Senior Director IP Cores Product Marketing, Rambus)

Location: Great America 3

Date: Wednesday, January 30

Time: 9:05am - 9:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD


Leading edge high-performance computation power and an exploding digital world is limited by memory speed, access throughput, and latency. This presentation discusses the various options available for enablement of a variety of applications, their characteristics, and tradeoffs.