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Xinjun Zhang (SI engineer, Intel Corp)
Mo Liu (SI engineer, Intel Corp)
Kai Xiao (SI engineer, Intel Corp)
Zhichao Zhang (SI engineer, Intel Corp)
Wenzhi Wang (SI engineer, Intel Corp.)
Yang Wu (SI engineer, Intel Corp.)
Location: Ballroom C
Date: Thursday, January 30
Time: 2:00pm - 2:40pm
Track: 13. Modeling & Analysis of Interconnects
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
A methodology to create minimally specification compliant behavioral models of connectors or sockets is proposed. Based on the physical structures of the component to be modeled, a behavioral model is constructed with a set of parametric coupled transmission lines, and major lumped component behaviors such as series inductors, and parallel capacitors and mutual elements at all the ports. These building elements are used to mimic the electrical performance, including the insertion loss, impedance profile/reflections, and the crosstalk, of the component. Those parameters are, then, optimized so that the resulting performance metrics meets the required limit lines minimally.
A methodology to create behavioral models of connectors or sockets that minimally comply to a given specification limit lines is proposed. Following the methodology, a behavioral model of PCIe 5.0 minimally compliant CEM specification connector is generated. The concept is also applicable to other NRZ and PAM4 interconnect model development.