designcon is part of the Informa Markets Division of Informa PLC
This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.
April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Ken Willis (Product Engineering Group Director - System-Level Analysis, Cadence)
Xin Chang (SI/PI/EMC Tech Lead Engineer, Meta)
Location: Mission City Ballroom B5
Date: Thursday, April 7
Time: 1:00 pm - 1:45 pm
Track: Sponsored Session
Format: Sponsored Session
Education Level: All
Pass Type: 2-Day Pass, All Access Pass, Expo Pass
Vault Recording: TBD
Audience Level: All
Compared with MIPI D-PHY, MIPI C-PHY does not require a separate clock lane, which helps improve EMI issues due to clock signal radiation and provides flexibility so that each lane can work independently. The 3-phase symbol encoding technology also enables higher data rates at a lower toggling frequency and with a smaller number of lanes and pins, further reducing power and cost.
According to our product design feature, our PCB design required lengthy routing between the SoC and camera. In one of our Engineering Development Boards (EDB), we observed SI loss and eye issues. To gauge the design risk and better understand MIPI C-PHY's practical SI feasibility and performance, we asked Cadence for help and worked with their EDA and SI experts to develop a general and powerful compliance toolkit for MIPI C-PHY simulation. In this presentation, we will show how we use this toolkit to investigate system-level design layout exploration and optimization for signal integrity using a real IBIS model (not generic) and a real PCB design, including the Common Mode Choke (CMC) effect. We will also show a live demo to familiarize the audience with the tool GUI and usage. We trust that it can easily help others implement MIPI C-PHY designs, including SI simulation and compliance checking.