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Mode Conversion & Its Impact on 112-Gbps PAM4 Systems

Jason Chan (Senior Principal Product Engineer, Cadence Design Systems, Inc.)

Hong Anh (Signal Integrity Engineer, Xilinx)

Geoff Zhang (Distinguished Engineer and Supervisor, Xilinx)

Min Huang (Design Engineer, Xilinx)

Location: Ballroom C

Date: Wednesday, January 30

Time: 8:00am - 8:45am

Track: 08. Optimizing High-Speed Serial Design, 14. Modeling & Analysis of Interconnects

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

As data rates tend to 112G PAM4, mode conversion becomes non-negligible as its impact is comparable to or even larger than other impairments. A simulation approach is proposed such that the mode conversion impact on the system margin is included, in contrast to the conventional method in which only pure differential signaling is modeled as facilitated by perfectly balanced and de-skewed transmit signals. Necessary changes to IBIS-AMI standards are proposed such that inclusion of mode conversion is optionally included. Detailed examples are provided to show the impact of mode conversion on link performance margin degradation.


Understand causes of mode conversion, manifestation of common mode in PAM4 transmitters and how to include them in existing simulation platforms. Necessary changes to IBIS-AMI standards to incorporate common mode Tx components and mode conversion effects are also proposed for the industry. The paper will provide detailed examples.

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