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DesignCon 2019 Presentation Viewer

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Modeling and Simulating 112G SerDes

Manuel Luschas (Signal Integrity Engineer, Cadence)

Ken Willis (Product Engineering Architect, Cadence)

Margaret Johnston (Systems Engineer, Cadence)

Location: Great America 3

Date: Thursday, January 31

Time: 2:00pm - 2:40pm

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD

Cadence Design Systems

With the demand for bandwidth skyrocketing, the Cadence IP division has recently announced availability of new PAM4 SerDes IP that will transmit and receive data rates as high as 112Gbps. These speeds spawn new challenges in terms of modeling and simulation. This session will cover the new challenges encountered in modeling and simulating these ultra-high speed PAM4 serial link interfaces, and how SystemSI and AMI Builder were employed to help address them.