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DesignCon 2019 Presentation Viewer

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Modeling and Simulation Challenges for 16Gbps GDDR6 Interfaces

Chung Huang (Design Engineering Director , Cadence)

Kancy Robison (Signal Integrity Engineer, Cadence)

Location: Great America 3

Date: Thursday, January 31

Time: 8:05am - 8:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD

Cadence Design Systems

As memory interface data rates climb to support performance demands, traditional interconnect / device modeling and simulation approaches become insufficient to meet the needs of pre-design feasibility and post-layout signoff analyses. GDDR6 interfaces push the envelope with data rates as high as 16Gbps, and utilize unique equalization capabilities that are challenging to model and simulate. In this presentation, hear from the Cadence IP team on these new challenges, and the methodologies employed to meet them.