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Modeling of Critical Crosstalk Paths for High Sampling Rate RF Direct Data Converters Integrated in a Programmable RF SoC

Brandon Jiao (Staff Transceiver Technical Marketing Engineer, Xilinx)

Romi Mayder (Senior Director of Technical Marketing, Xilinx)

Ntsanderh C Azenui (Senior Application Engineer, Ansys)

Andrew Wang (Application Engineer Manager, Ansys)

Location: Ballroom G

Date: Wednesday, January 30

Time: 2:00pm - 2:40pm

Track: 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Traditional crosstalk depression technics such as using stripline, setting routing space between traces and providing vertical return paths for layer transition vias and package/ connector signal pins are well applied in transceiver applications. Though these methods provide enough isolation for 100GE CR4/KR4, they are far away from meeting the isolation requirement in RF applications of -100dB noise floor. This gap must be mitigated when SI engineers design RF direct sampling systems with RFSoC integrated with both transceivers and RF ADC/DACs. This paper introduces the new crosstalk depression methodology and analysis based on 3D fields simulation with ultra-low noise floor.

Takeaway

The vertical return path is critical to minimize the crosstalk received at RF ADC/DAC. Co-optimization including flip chip BGA package, PCB stackup and routing, vias and RF connector pin map is a must to
meet the crosstalk requirement in the cost driven RF applications

Presentation Files

SLIDES_06_ModelingofCriticalCrosstalkPaths_Jiao.pdf
PAPER_06_ModelingofCriticalCrosstalkPathsfor_Jiao.pdf