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Modeling System Signal Integrity Dynamic to Achieve Optimal Memory Performance for DDR4 & Beyond

Hing "Thomas" To (Director, Xilinix)

Changyi Su (Staff Engineer, Xilinx)

Juan Wang (Senior Staff Engineer, Xilinx)

Location: Ballroom B

Date: Wednesday, January 30

Time: 11:00am - 11:45am

Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Modeling effective bandwidth is crucial in determining performance as system memory scales to top speed DDR4 and beyond. This paper will present a new approach to cover DDR bus turnaround dynamic. The DQ bus on the controller side and the DRAM is modeled with IO behavioral model which captures the On/Off timing. Details will be presented on how to handle the necessary feature for the modeling. This approach enables the prediction of bus channel dynamics, particularly in the case of turnaround signal integrity analysis in rank-to-rank switching between DIMMs. A validation system will be used to correlate this approach.


Modeling bus turnaround with signal integrity is crucial as memory capacity and speed scales to top speed DDR4 and beyond. The approach presented in this paper enables system designers to evaluate tradeoffs with signal integrity consideration. Also, this approach allows accurate memory bandwidth prediction & modeling.

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