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Modular Platform Design & Optimization for PCIe 5.0 IPs Validation

Xiao-Ming Gao  (Engineer, Intel Corporation)

Peng Z Yang  (Engineer, Intel Corporation)

Jianmei X Zhu  (System Architect and Technical Lead, Intel Corporation)

Guoyu (Stan) Yang  (Engineer, Intel Corporation)

Location: Ballroom B

Date: Wednesday, January 29

Time: 2:00pm - 2:40pm

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Optimizing High-Speed Serial Design

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

A modular platform architecture is proposed to validate PCIe 5.0 IPs. This platform consists of a universal baseboard (UBB), a universal power card (UPC), a universal control card (UCC), and a personality card (PC). The PC is installed on top of the UBB using board to board connectors through which power, clock, and controls signals are delivered to the silicon on the PC from UBB, UPC, and UCC. The UPC provides programmable power rails with different voltage levels and UCC with on-board FPGA provides power-on sequencing to UPC and UBB. The platform is reconfigurable and scalable with future high-speed I/Os.


The modular platform was successfully used to validate SoC testchip with PCIe 5.0 IP and able to achieve first power on success. The measurement data show the platform performance exceeds design requirements. The platform can be used for PCIe 5.0 and beyond high speed I/O platform designs and validations.

Presentation Files