DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!


DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

New Characterization Techniques for DDR5 Memory Generation and Beyond

Saifee Jasdanwala (Memory Solution Marketing Engineer, Tektronix)

Location: Mission City M1

Date: Wednesday, January 30

Time: 2:00pm - 2:40pm

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD

Tektronix

With the 5G standard knocking on the door, datacenters will need to access a large amount of data at faster speeds and lower the power consumption at the same time. DDR5 provides double the bandwidth and density over DDR4 and delivers improved channel efficiency. Join Tektronix as we provide an update on the latest characterization and debug techniques to enable analysis of the highest DDR5 speed grades.

Our presentation will cover:
• New DDR5 receiver compliance test
• New capabilities such as a 4 tap decision feedback equalizer (DFE) for DDR5 and why they are being considered.
• Probing techniques to access the signals on the DRAM interface.
• Full channel de-embedding to remove the effects of the interposer and observe the signal at the die.
• Tools to enable you to quickly capture, identify, analyze and characterize the memory interface.
• What to expect from a debug and validation perspective for next generation memory.

Intended Audience