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New Characterization Techniques for DDR5 Memory Generation and Beyond

Saifee Jasdanwala (Memory Solution Marketing Engineer, Tektronix)

Location: Mission City M1

Date: Wednesday, January 30

Time: 2:00pm - 2:40pm

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD


With the 5G standard knocking on the door, datacenters will need to access a large amount of data at faster speeds and lower the power consumption at the same time. DDR5 provides double the bandwidth and density over DDR4 and delivers improved channel efficiency. Join Tektronix as we provide an update on the latest characterization and debug techniques to enable analysis of the highest DDR5 speed grades.

Our presentation will cover:
• New DDR5 receiver compliance test
• New capabilities such as a 4 tap decision feedback equalizer (DFE) for DDR5 and why they are being considered.
• Probing techniques to access the signals on the DRAM interface.
• Full channel de-embedding to remove the effects of the interposer and observe the signal at the die.
• Tools to enable you to quickly capture, identify, analyze and characterize the memory interface.
• What to expect from a debug and validation perspective for next generation memory.

Intended Audience