April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Next Generation 224Gbps-PAM4 SERDES, Channel & Link Systems


Mike Li  (Fellow, Intel)


Hsinho Wu  (Design Engineer, Intel)

Masashi Shimanouchi  (Design Engineer, Intel)

Jenny Jiang  (Principal Engineer, Intel)

Zhiguo Qian  (Principle Engineer, Intel)

Ajay Balankutty  (Principal Engineer)

Itamar Levin  (Principal Engineer)

Ariel Cohen  (Senior Principal Engineer)

Stas Litski  (Team Leader of the Signal and Power Integrity)

Location: Ballroom H

Date: Wednesday, April 6

Time: 12:15 pm - 1:00 pm

Track: 09. High-Speed Signal Processing, Equalization & Coding/FEC

Format: Technical Session

Theme : High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

In our 2021 Designcon paper [1], we have conducted comprehensive silicon correlated simulations and modeling for chip-to-module (C2M) and chip-to-chip over backplane (BP)/long reach (LR) at 224 Gbps, for PAM4, PAM6, and PAM8 modulations. We have found that for LR/BP channels with end-to-end (E2E, or bum-to-bump) insertion loss (IL) < 40 dB, PAM4 outperforms PAM6 and PAM8, and we concluded that PAM4 would be the optimal modulation of choice due to its natural backward and optical compatibility and overall lowest cost and power for host-to-host links involving optical or passive cable or BP/LR channel medium. In this paper, we will: 1.) focus on C2M and BP/LR E2E (from package, to package break-out, to landing-pad, via/connector, and PCB/cable) channel technology advancements which enable PAM4 modulation for the required performance and solution space; 2.) conduct systematical time-domain waveform bit-by-bit and COM simulations using the further improved silicon and package parameters that are consistent with our latest 224 Gbps-PAM4 test chip; 3.) investigate FEC coding gain (CG) and performance boost options, such as RS(544,514) + BCH (soft decision or hard-decision) concatenation, in case if stronger FEC is needed is needed for relaxing the pre-FEC BER or to insure the 1e-15 post FEC BER with margin/robustness.


This paper presents the latest 224 Gbps-PAM4 E2E channel and 224 Gbps-PAM4 SERDES silicon technology advancements and demonstrates E2E solution space meeting the needed performance requirement.

Intended Audience

For audience with knowledge on high-speed I/O and links, channel physics, SERDES, modulations, FEC, and link performance.