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Noise Modeling & Simulations in 112-Gbps PAM4 Serial Links

Hsinho Wu (Design Engineer, Intel Corp)

Mike Li (Fellow, Intel Corp)

Masashi Schimanouchi (Design Engineer, Intel Corp)

Location: Ballroom E

Date: Wednesday, January 29

Time: 2:00pm - 2:45pm

Track: 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC), 07. Optimizing High-Speed Serial Design

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

In serial links, signal is generated, transmitted, and shaped by link components, such as drivers, channels, and equalizers. Likewise, noises, e.g. reference clock phase noises, power supply noise …etc., go through the same transforming processes. In <25Gbps links, while jitter, i.e. timing noises, is extensively studied and modeled, other noises, except channel crosstalk, are mostly neglected because NRZ links are usually constrained by timing budget. In >50Gbps PAM4 links, which are constrained in both timing and amplitude budgets, accurate noise modeling becomes critical in accessing link margins. In this paper, we will explain noise characteristics and investigate noise modeling techniques.

Takeaway

The audience will gain the knowledge on noise source and characteristics within high-speed serial links as well as modeling techniques.

Intended Audience

For audience with knowledge on high-speed serial links, jitter and noise components, and equalization schemes in serial communication links.