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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Mukesh Moorthy (Analog Engineer, Intel)
Manjunath J (Analog Engineer, Intel)
Location: Ballroom F
Date: Thursday, April 7
Time: 2:00 pm - 2:45 pm
Track: 10. Power Integrity in Power Distribution Networks, 06. System Co-Design: Modeling, Simulation & Measurement Validation
Format: Technical Session
Theme : High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
Multiple High-speed Serial IOs working upto 32G with shared voltage-regulator demands very tight package/silicon design and more stringent power supply noise specification per each HSIO. Failing to meet strict PDN noise spec would result in functional/compliance failure and violate jitter specifications. This poses lot of challenges to meet the design spec at platform, voltage-regulator, board, package and die level. Attaining the voltage regulator spec which caters multi-HSIO connected to the same voltage regulator is a herculean task and in turn reduces the BOM cost. This paper demonstrates real time power delivery network design enforcing methodical ways in designing full chip floorplan, decoupling solution for board, package, die and power delivery planning within the IO and isolation strategy with highest accuracy in multi-IO systems, in-turn meeting HSIO PDN design spec requirements working at 32G & beyond. Further co-relating the PDN data with post silicon values which covers the measurement at package probe & co-relation on the die capacitance is shown in detail.
Isolation of power rails at package, PDN modeling along with on-die cap would result in meeting noise specification for multi HSIO IP working in same voltage-regulator. With proposed methodology coupling-noise from the non-critical IP to critical IP can be eliminated, on-die cap and power-supply noise was co-related in post-silicon.