April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Onchip ESD Protection Structure Modeling Methodology


Zhekun Peng  (PhD Student, EMC Laboratory, Missouri S&T)


DongHyun Kim  (Assistant professor, EMC laboratory, Missouri S&T)

Location: Ballroom E

Date: Wednesday, April 6

Time: 8:00 am - 8:45 am

Track: 11. Electromagnetic Compatibility & Interference

Format: Technical Session

Theme : Security

Education Level: Introductory

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: Introductory

Electrostatic discharge (ESD) events can result in soft and hard failures to an integrated circuit (IC). To protect the ICs from ESD, ESD protection structure is critical for chip-level design. Since chip-level internal ESD protection circuit information is often not released to the public, we propose a modeling methodology based on transmission line pulse (TLP) measurement to accurately obtain both quasi-static current-voltage (IV)-curves and small signal model of the on-chip ESD protection structure, for the first time. The proposed methodology uses vector network analyzer (VNA), source meter unit (SMU), and TLP to characterize the small signal model and large signal model for all possible ESD protection diodes inside the ICs. Special test jig having connection between including Power-to-Ground, Signal-to-Ground and Signal-to-Power is designed for different ICs. Our proposed measurement-based IC ESD protection modeling is verified by simulation and measurement results on multiple ICs. Our proposed model can be further used in optimizing the system-level ESD protection without information on internal IC ESD protection scheme.


This paper proposes, for the first time, the modeling methodology of on-chip ESD protection structure for different types of IC pins without the access to IC inner structures. The modeling process for both small and large signal models are provided and verified with different ICs in both measurement and simulation.