DesignCon 2022 Schedule Builder

With the ever-increasing demand for both high-performance and low-power mobile phone, it is becoming more and more difficult to meet the SI/PI-related target specifications. This problem can be further aggravated as the supply voltage of Low Power Double Data Rate (LPDDR) memory in mobile decreases from 1.1 V down to 1.05 V for LPDDR5, possibly resulting in more logic malfunctions of the system. In order to mitigate these problems, Power Management Integrated Circuit (PMIC) and many Decoupling Capacitors (decap) are mounted on the board of mobile to enhance the PI performance. Accordingly, to find the optimal decap combination with prediction of Power Integrity (PI) characteristics has become important for minimum Simultaneous Switching Noise (SSN). To predict mobile board-level voltage ripple (AC) and IR drop (DC) characteristics, an accurate evaluation of PMIC characteristics is of utmost importance. In this paper, a novel methodology for optimal decap design using Q-learning algorithm and for accurate analysis of mobile board-level PI performance, which includes nonlinear PMIC characteristics along with other power models of passive components and Chip Power Model (CPM) is proposed. Through a series of simulations in both time and frequency domains, we successfully verified the accuracy of the proposed optimization and prediction methodology and proved its high practicality.