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Overcoming DDR5 Simulation Challenges

John Ellis (Principal Engineer, Synopsys, Inc.)

Location: Ballroom F

Date: Thursday, January 31

Time: 8:00am - 8:45am

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

The DDR5 standard introduces several challenges to simulating link performance completely and efficiently. Dual DIMM applications require DFE to decipher reflections to hit bit rates of 4400Mbps and higher. During Writes, unmatched DQS and DQ delays, remove beneficial jitter tracking and complicate eye capture in simulation. Finally, the interface must be characterized to a BER of 1E-16. All of this occurs in a highly nonlinear environment dominated by single-ended SSO events. This paper demonstrates an efficient DDR5 simulation methodology capturing SSO timing impacts and DFE effects in a statistical simulator, allowing characterization at low BER.


Methodology to capture non-linear timing impacts from SSO in a statistical simulator.
Better understanding of DDR5 requirements
Inclusion of DFE effects in a statistically generated eye pattern.
Realistic inclusion of simulated results in a DDR5 timing budget.

Presentation Files