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Panel – 112-Gbps Package Challenges

Hsinho Wu (Designer Engineer, Intel Corp.)

Masashi Shimanouchi (Design Engineer, Intel Corp.)

Adee Ran (Principal Engineer, Intel)

Richard Mellitz (Distinguished Engineer , Samtec)

Yuriy Shlepnev (President , Simberian Inc.)

Mike Resso (Signal Integrity Application Scientist, Keysight Technologies)

Location: Ballroom G

Date: Tuesday, January 29

Time: 4:45pm - 6:00pm

Track: 05. Advances in Materials & Processing for PCBs, Modules & Packages, 08. Optimizing High-Speed Serial Design

Session Type: Panel Discussion (Free)

Vault Recording: TBD

Audience Level: All

100Gbps Ethernet (IEEE 802.3ck) and OIF CEI 112Gbps specifications have pushed the Nyquist frequencies to 26.56GHz and 28GHz. This means that device and system vendors need to re-evaluate their bandwidth requirements and link configurations such as: reduction of channel budget due to extra insertion loss consumed by packages, device/package/PCB co-optimizations, package impedance choices, and consideration of package's PVT variations. In this panel, we would like to discuss the impacts, challenges, technology outlook, and solutions with experts from various areas including device/package design, standards, test and measurement, system builders, and 3D EM modeling.

Takeaway

The audience will gain the knowledge on package requirements and challenges at 112Gbps and beyond.