April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Panel – AMI Models & the Seven-year Itch
Moderator:
Donald Telian (SI Consultant, SiGuys)
Panelists:
Walter Katz (Chief Scientist, MathWorks)
Randy Wolff (Principal Engineer, Micron)
Aleksey Tyshchenko (CEO, Founder, SeriaLink Systems)
Michael Mirmak (Applications Engineering Manager, Intel)
Ken Willis (Product Engineering Architect, Cadence)
Location: Ballroom AB
Date: Tuesday, April 5
Time: 4:45 pm - 6:00 pm
Track: 02. Chip I/O & Power Modeling, 07. Optimizing High-Speed Link Design
Format: Panel Discussion
Theme : Data Centers, High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass, Expo Pass
Vault Recording: TBD
Audience Level: All
Though IBIS-AMI models have delivered on their original mission of modeling SerDes equalization, is the standard adequately adapting and expanding? Standard developers may have assumed AMI's executable format is extensible by design, but is that true for challenges like DDR5 and 112 Gbps SerDes? Are the new problems and technologies users care about getting solved? Will AMI have the longevity to handle the future? Join DesignCon's 7th yearly – and markedly itchier – AMI Panel Discussion as experts provide answers to the hard questions about what is working, and not working, with AMI.
Takeaway
* Extensibility of the AMI standard, practically and technologically
* How AMI models and analysis are adapting to handle 112 Gbps and DDR5
* AMI's upstream reach into standards, architecture, and design exploration
* An honest "report card" on how the standard is working, now and in the future
Intended Audience
Attendees should have an interest in or understanding of serial links, AMI models, SerDes/Serial and/or DDRx simulation, and analysis tools.
