April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Panel – CXL & PCIe Technologies: The Next Generation of Interconnects
Moderators:
Scott Knowlton (Director, Strategy & Solutions, Synopsys)
Kurt Lender (Senior Ecosystem Enabling Manager, Data Center Group, Intel)
Panelists:
Ishwar Agarwal (Principal Hardware Engineer, Microsoft)
Mohiuddin Mazumder (Senior Principal Engineer, Intel)
Location: Ballroom EF
Date: Tuesday, April 5
Time: 4:45 pm - 6:00 pm
Track: 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 07. Optimizing High-Speed Link Design
Format: Panel Discussion
Theme : Data Centers
Education Level: All
Pass Type: 2-Day Pass, All Access Pass, Expo Pass
Vault Recording: TBD
Audience Level: All
Datacenter architectures are evolving to support the workloads of emerging applications in Artificial Intelligence and Machine Learning that require a high speed, low latency, cache coherent interconnect.
The Compute Express Link™ (CXL™) specification address the challenges brought by heterogeneous computing and delivers breakthrough performance while leveraging PCI Express® (PCIe®) technology to support rapid adoption. CXL enables a high-speed, efficient interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions. CXL 2.0 specification addresses resource sharing, switching for system expansion, memory pooling for increased efficiencies, support for persistent memory and maintains full backward compatibility.
Over the past three decades, PCI-SIG has delivered a succession of industry-leading specifications that remain ahead of the curve of the increasing demand for a high-bandwidth, low-latency interconnect for compute-intensive systems in diverse market segments. The PCIe 6.0 specification – targeted for final release in 2021 – will deliver 64 GT/s data rate, while maintaining backward compatibility with previous generations.
The CXL™ Consortium and PCI-SIG® established a memorandum of understanding (MOU) between the two organizations. In this technical panel, industry experts from both organizations will explore the next generation of interconnects featuring PCIe and CXL technologies.
Takeaway
• Gain insight into the CXL 2.0 specification, CXL technology and PCIe 6.0 technology
• Understand the next generation of interconnects featuring PCIe and CXL architectures (26 words)
