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Panel – Enabling New Architectures: An Update on OIF's CEI-112G Electrical Interfaces

Nathan Tracy  (Technologist, TE Connectivity)

Cathy Liu  (Distinguished Engineer and Director, Broadcom Inc.)

Steve Sekel  (400G/800G Solutions Specialist, Keysight Technologies)

Ed Frlan  (Senior System Architect, Semtech)

Gary Nicholl  (Principal Engineer, Cisco)

Mike Li  (Fellow, Intel)

Location: Ballroom F

Date: Wednesday, January 29

Time: 3:45pm - 5:00pm

Track: 07. Optimizing High-Speed Serial Design

Format: Panel Discussion

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Electrical interfaces at 112 Gbps are a critical enabler of faster, more efficient and cost effective networks and data centers. A panel of OIF contributors will discuss the ongoing CEI-112G electrical interface development projects, and the new architectures they will enable including chiplet packaging, co-packaged optics and internal cable based solutions. The panel will provide an update on the multiple interfaces being defined by the OIF including CEI-112G MCM, XSR, VSR, MR and LR for 112 Gbps applications of die-to-die, chip-to-module, chip-to-chip and long reach over backplane and cables. Listen to thought leaders in the electrical interface industry debate the issues surrounding the CEI-112G projects and the architectures they will enable.


OIF is developing 112 Gbps interoperable electrical interfaces that will enable faster, efficient and cost effective networks and data centers. Get an update on the new architectures these interfaces will enable. Five new interfaces will shape the future of next generation designs, ranging from die to die implementations all the way up to backplane and copper cable architectures.

Intended Audience

No prerequisites

Presentation File