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Panel – PCI Express Ecosystem: Getting Ready for 32 GT/s

Steve Krooswyk (New Connector SI Design, Samtec)

Pegah Alavi (Senior Applications Engineer, Keysight)

Rita Horner (Sr. Technical Marketing Manager, Synopsys)

Mo Liu (PCIe SI Lead, Intel)

Rick Eads (Principal PCI Express Program Manager, Keysight)

Dean Gonzales (SI Lead, AMD)

Alfred Key (PCIe Product Architect for Board and Systems, NVIDIA)

Location: Ballroom C

Date: Wednesday, January 30

Time: 3:45pm - 5:00pm

Track: 08. Optimizing High-Speed Serial Design

Session Type: Panel Discussion (Free)

Vault Recording: TBD

Audience Level: All

The PCI Express ecosystem will soon make a generational leap, doubling to 32GT/s. Our panel highlights the challenges in designing, implementing, and validating a new generation of PCI Express. We review the critical silicon to silicon questions: Is Gen5 PHY destined to use more DFE and more power? How to navigate controller and switch options? How do I know a cable or connector is 32G capable? What scope BW is required? Is the package more important at 32G? What channel optimization is needed? What potential add in card improvements?

Takeaway

As PCI Express speeds increase, so do the challenges. The attendees will gain important insights from leading experts in the design, implementation, and validation for PCI Express at 32GT/s.