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Panel – PCIe 32G & 64G: System Design & Test Challenges

Steve Krooswyk (New Product and Standards SI, Samtec)

Rita Horner (Technical Marketing Manager, Sr. Staff, Synopsys)

Ying Li (SI/PI Engineer, NVIDIA)

Dan Froelich (Director of Systems Engineering, Tektronix)

Pegah Alavi (Director, Keysight)

Patrick Casher (Pr. Product Development Engineer, Foxconn Interconnect Technology)

David Bouse (Systems Engineer, Tektronix)

Rick Eads (Principal PCI Express Program Manager, PCISIG Board Member, Keysight)

Tim Wig (Signal Integrity Engineer, Intel)

Location: Ballroom F

Date: Thursday, January 30

Time: 3:45pm - 5:00pm

Track: 07. Optimizing High-Speed Serial Design

Format: Panel Discussion

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

As PCI Express 5.0 system development commences, 64G-PAM4 has been announced to follow in 2 years. Join our panel to discuss the challenges in PCIe 5.0\6.0 system designs and validation. We will address key questions: Is 85 ohm PCB, connector, or cable required? How critical is system crosstalk at PAM4? How does new Integrated Crosstalk Noise for connector compliance work? What is new in post-silicon validation? How is the gold finger design changing? Possible requirements for add in cards? Is microstrip dead?

Takeaway

Understand the design and validation challenges at 32GT/s NRZ and 64GT/s-PAM4. Come away equipped to make better decisions for packages, systems, connectors, and add in cards.