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Panel – Succeeding with Next-Generation AMI Models & Analysis

Donald Telian  (SI Consultant, SiGuys)

Ken Willis  (Product Engineering Architect, Cadence)

Stephen Scearce  (Sr. Engineering Manager, Cisco)

Walter Katz  (Chief Scientist, MathWorks)

Hsinho Wu  (Design engineer , Intel)

Justin Butterfield  (Senior Engineer, Micron)

Location: Ballroom D

Date: Wednesday, January 29

Time: 3:45pm - 5:00pm

Track: 02. Chip I/O & Power Modeling & Validation Solutions, 07. Optimizing High-Speed Serial Design

Format: Panel Discussion

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

IBIS-AMI models are the ubiquitous choice for the most challenging simulation tasks. This yearly Panel addresses topics you need to understand to succeed with next-generation AMI models and analysis. Originally developed to model the Gigabit SerDes, the standard is adapting to handle new challenges such as DDR5 and PAM4. What's new in SerDes equalization and its back-channel optimization? What changes are necessary for 112 Gbps? How is the "clock" applied in DDR5 since it doesn't travel inside the data? Join us for another insightful discussion with AMI experts and learn timely answers to these questions and more.


* What you need to know to succeed with the new applications for AMI
* How AMI models and analysis are adapting to handle DDR5
* Considerations for modeling and designing 112 Gbps PAM4 interfaces
* Changes in SerDes equalization, and back-channel programming of the same

Intended Audience

Attendees should have an interest in or understanding of serial links, AMI models, SerDes/Serial and/or DDRx simulation, and analysis tools.

Presentation File