April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Parametric System Model of a 112Gbps ADC-based SerDes for Architectural, Design & Validation Project Phases


Aleksey Tyshchenko  (CEO, Founder, SeriaLink Systems)


David Halupka  (Founder & Director, SeriaLink Systems)

Venu Balasubramonian  (Senior Director, Product Marketing, Marvell Semiconductor)

Lenin Patra  (VP/Marvell Fellow, Marvell Semiconductor)

Location: Ballroom D

Date: Wednesday, April 6

Time: 12:15 pm - 1:00 pm

Track: 02. Chip I/O & Power Modeling, 07. Optimizing High-Speed Link Design

Format: Technical Session

Theme : High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

This paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases: from architectural definition, through analog and digital design, to validation.

Modeling techniques that enable a single model to support a wide range of system modeling activities are introduced. The parametrization of key design variables allows for the evaluation of architectural options to generate block level specifications. Object oriented modeling is used to decouple block interfaces from the evolving block implementation, thereby maintaining a simulation-ready top-level model. The block-level models support automated export to SystemVerlilog thereby facilitating mixed-signal design validation.

A correlation example is described to illustrate how the proposed modeling framework can be configured to reflect the IBIS-AMI model of a 112Gb/s ADC-based SerDes product.

In addition to being a valuable tool during SerDes development, these models can be delivered to system integrators enabling the incorporation of accurate models that capture the details of a real-life ADC-based SerDes right from the feasibility study phase. These models allow system integrators better observability and flexibility in performing end-to-end link analysis: including simulation of co-packaged and opto-electrical systems, and exploring interaction between SerDes and FEC. The underlying implementation can be obfuscated at different hierarchy levels for IP protection.


A unified system modeling framework is presented. Participants will gain knowledge that with a little bit of up-front effort, system modeling can be structured such that a single model can span the SerDes development cycle from conception to validation. This eliminates the potential for model divergence or the overhead of correlation, which is typical when multiple single-use models are used.