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Partitioning of TX & RX Feedforward Equalizer for 112-Gbps Serial Links

Kevin Zheng (Staff Mixed Signal Design Engineer, Xilinx Inc.)

Boris Murmann (Professor, Stanford University)

Hongtao Zhang (Senior Staff Design Engineer, Xilinx)

Geoff Zhang (Distinguished Engineer and Supervisor, Xilinx)

Location: Ballroom G

Date: Wednesday, January 30

Time: 2:50pm - 3:30pm

Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

Effective utilization of FFEs on both the TX and RX sides plays an important role in enabling 112G systems. While TX FFE is limited by peak power constraint and RX FFE amplifies input noise, the optimal partitioning of FFE on both ends of the transceiver become a crucial design choice that will impact both system performance and power consumption. To provide a more realistic and complete framework, this paper offers a more fundamental analysis and understanding of TX/RX FFE partitioning in the presence of CTLEs and DFE.


An optimal TX and RX FFE partitioning will be a valuable tuning knob in pushing system performance while minimizing power consumption. FFEs' interactions with CTLE and DFE also needs attention, especially when moderate resolution converters are used. This work serves as a more complete framework for determining future system architecture.

Intended Audience

1. Basic concept of link equalization
2. Basic idea of link system modeling
3. Statistical signal processing

Presentation Files