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PCI Express 5.0 Solution Extending Study Through PCB Stackup & Geometry Optimization

Harrison Fei Xue (SI engineer, Intel)

Xinjun Zhang (SI engineer, Intel)

Yanwu Wang (SI engineer, Intel)

Location: Ballroom F

Date: Wednesday, January 29

Time: 11:00am - 11:45am

Track: 07. Optimizing High-Speed Serial Design, 13. Modeling & Analysis of Interconnects

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

HSIO solution space is shrinking as speed goes higher and higher even after applying upgraded and higher cost PCB materials. Three enablers based on stackup and geometry are analyzed, which includes copper thickness, core and prepreg thickness, and differential routing trace width and spacing. By applying these enables and together with a pitch-varied routing strategy and far-end crosstalk mitigation technique, a real PCB routing case study on a PCIe 5.0 channel is analyzed and up to 2.8 inches (28%) solution space extension is seen after using 5-mil core and pitch-varied routing.

Takeaway

As signaling speed goes high, maximum allowed channel length actually shrink even after applying the upgraded PCB materials. By applying three proposed enablers, a pitch-varied routing strategy and far-end crosstalk mitigation technique, we are able to see up to 2.8 inches (28%) solution extension for a real PCIe 5.0 application.

Intended Audience

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