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PCI Express Rockets Forward to 64GT/s: Phy Layer Testing Challenges at 32G NRZ and 64G PAM4

Rick Eads (Principal Program Manager for Serial Computer Bus Technologies, Keysight Technologies)

Pegah Alavi (Director, Keysight)

Location: Great America 1

Date: Wednesday, January 29

Time: 11:05am - 11:45am

Track: Keysight Education Forum

Vault Recording: TBD

Technologies such as 800G Ethernet (IEEE 802.3ck, OIF CEI-112G) are driving I/O interconnect technologies such as PCI Express to 64GT/s in the 6th generation of that standard. Concurrent computing needs which are elevating coprocessor components to the same computer architectural hierarchy as the CPU are being developed in the Compute Express Link (CXL) and Cache Coherent Interconnect for Accelerators (CCIX) Consortiums and are reaching speeds of up to 32GT/s and looking to go even faster. With this increase in digital transmission speed, the increase in throughput is accompanied by significant signal integrity challenges related to transmitter signal quality, connector crosstalk, receiver jitter sensitivity, and overall channel insertion loss around the Nyquist frequency at which each of these standards operate. In this session, we will bring you the latest information on what Keysight is doing to help develop standards like PCI Express 6.0 and other similar standards as far as physical layer testing including transmitter, receiver, and channel testing. In addition, we will describe the latest approach to achieving compliance that uses the same software tools you use for device characterization but using data provided by simulation instead of physical measurement. The simulation mimics a real hardware test bench, and it emits the same waveforms that the oscilloscope app expects when testing in the lab. This allows you to verify the pre-manufacture simulated design with the actual post-manufacture prototype.