April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

DesignCon 2022 Schedule Builder


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PCIe 6.0 & Beyond: PAM4 Burst BER & Jitter Tolerance Test with FEC Uncorrectable Error Analysis

Speaker:

Hiroshi Goto  (Sr. Market Development Manager, Anritsu)

Location: Great America Meeting Room 1

Date: Thursday, April 7

Time: 11:15 am - 12:00 pm

Track: Sponsored Session

Format: Sponsored Session

Education Level: All

Pass Type: 2-Day Pass, All Access Pass, Expo Pass

Vault Recording: TBD

Audience Level: All

High-speed and large-capacity transmission standards using PAM4 signaling, such as PCIe 6.0 and 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality. The session will focus on PAM4 BER and jitter tolerance tests for SERDES, DSP, and CDR used by transceivers where the pre-FEC evaluation of bit error rate performance is required as well as correctable/uncorrectable FEC symbol error performance.