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PCIe Gen 5 CEM Connector & Add-In Card PCB Design Optimizations

Ying Li (SI/PI engineer, NVIDIA)

Yifan Huang (SI Team Lead , Amphenol)

Stephen Smith (Senior Staff SI Engineer, Amphenol)

Alfred Key (PCIe Product Architect for Board and Systems, NVIDIA)

Abhijit S. Wander (Senior Signal Integrity Engineer, Amphenol Corporation)

Liu He (Senior Signal Integrity Engineer, Amphenol Corporation)

Yaping Zhou (SI/PI Manager, Nvidia Corporation)

Location: Ballroom A

Date: Wednesday, January 30

Time: 2:50pm - 3:30pm

Track: 14. Modeling & Analysis of Interconnects, 08. Optimizing High-Speed Serial Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

The PCIe Gen5 channel data-rate of 32GT/s requires a better mating connector, an AIC with improved PCB material, optimized vias, and alternative trace routings. The Gen5 surface-mount connector mates with the smaller gold edge fingers with a shorter wipe distance to achieve loss and crosstalk targets at twice the Gen4 Nyquist frequency. AIC microstrip or stripline routings, via choices, ac capacitor mounting, and their effects are optimized for overall channel performance. AIC lead-in trace region to the connector is re-designed to improve the impedance match to the CEM connector. Measurements of a connector prototype with improved AIC validate the work.


The PCIe Gen5 Card Electro-Mechanical (CEM) connector is backward-compatible and mates to an Add-In Card (AIC) with smaller edge fingers that have a shorter wipe distance. AIC design choices between microstrip and stripline traces are made to balance loss, crosstalk and mode conversion for optimizing the full channel performance.

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