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PDN Complexities & Design Strategy for Serdes Interfaces in Automotive/Workstation Applications

Nithya Sankaran (Senior Signal Integrity Engineer, Nvidia Corporation)

Prathap Muthana (Senior Signal Integrity Engineer, Nvidia Corporation)

Sunil Sudhakaran (Director, Signal Integrity, Nvidia Corporation)

Location: Ballroom B

Date: Wednesday, January 30

Time: 2:50pm - 3:30pm

Track: 11. Power Integrity in Power Distribution Networks, 04. System Co-Design: Modeling, Simulation & Measurement Validation

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

High bandwidth data transfer requirement for automotive and
workstation platforms is presenting increased challenges for
Power Delivery Network (PDN) design for serdes interfaces.
Pre-silicon budget of voltage margin needs to include
multiple factors such as process and temperature related
voltage derating, DC drop and switching noise across chip,
package and PCB. Budgeting should also be cognizant of the
minimum voltage required to meet timing for digital blocks
of serdes interfaces and their controllers. This paper
discusses accounting of voltage budget parameters, selection
of lowest voltage for satisfying timing requirements and
presents a flow to integrate on-chip power grid in switching
noise evaluation.


High Bandwidth, Automotive use-case, serdes power rail, voltage margin, pre-silicon voltage budget, digital timing corner selection, on-chip power grid model, GHz range switching noise

Presentation Files