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PDN Induced Jitter Analysis in High Speed NAND Flash Memory Interface

Sayed Mobin (Director, Hardware Development Engineering, Western Digital)

Location: Ballroom B

Date: Wednesday, January 29

Time: 2:50pm - 3:30pm

Track: 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 10. Power Integrity in Power Distribution Networks

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

The Power Delivery Network (PDN) of the NAND Flash silicon characterization environment contributes significant random jitter in NAND clock signals (DQS/BDQS) duty cycles. The specification values for the clock pulse width is used in signal integrity (SI) simulation, include both the average duty cycle distortion and the typical duty-cycle jitter. PDN also contributes random jitter in the data lines resulting in bit to bit skew within a byte. This paper identifies PDN jitter impact on the critical NAND AC timing parameters and describes how to correctly implement NAND AC timing parameter specifications for more accurate system level performance prediction.

Takeaway

Will address following two Questions

1) It is established that RE DCD needs to be included in SI Simulation, Why do we need to modify the proposed method?

2) NAND AC timing parameters are determined through a standard process, why do we need to make adjustment to the spec values during system level analysis?

Intended Audience

Understanding of Basic Transmission line theory, Power Distribution Network, Jitter concept, Characterization environment, Basic NAND Flash memory Interface