DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

PDN Induced Jitter Analysis in High Speed NAND Flash Memory Interface

Sayed Mobin  (Director, Hardware Development Engineering, Western Digital)

Venkatesh Ramachandra  (Director, Western Digital)

Pranav Balachander  (Staff Engineer (SIPI Hardware Development Engineering), Western Digital)

Jiwang Lee  (Staff Design Engineer)

Chau D. Nguyen  (Electrical Engineer, Western Digital)

Asha Sharma  (Manager, Electronic Design, Western Digital)

Location: Ballroom B

Date: Wednesday, January 29

Time: 2:50 pm - 3:30 pm

Track: 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 10. Power Integrity in Power Distribution Networks

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

The Power Delivery Network (PDN) of the NAND Flash silicon characterization environment contributes significant random jitter in NAND clock signals (DQS/BDQS) duty cycles. The specification values for the clock pulse width is used in signal integrity (SI) simulation, include both the average duty cycle distortion and the typical duty-cycle jitter. PDN also contributes random jitter in the data lines resulting in bit to bit skew within a byte. This paper identifies PDN jitter impact on the critical NAND AC timing parameters and describes how to correctly implement NAND AC timing parameter specifications for more accurate system level performance prediction.


Will address following two Questions

1) It is established that RE DCD needs to be included in SI Simulation, Why do we need to modify the proposed method?

2) NAND AC timing parameters are determined through a standard process, why do we need to make adjustment to the spec values during system level analysis?

Intended Audience

Understanding of Basic Transmission line theory, Power Distribution Network, Jitter concept, Characterization environment, Basic NAND Flash memory Interface

Presentation Files