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Performance-Driven Voltage Regulator Module Specification for Optical Transport Network

Xiaoping Liu (Analog Engineer, Intel Corporation)

Dong-Myung Choi (Circuit Designer, Intel Corporation)

Ron Ho (Director, Intel Corporation)

Wendem Beyene (Principal Engineer, Intel Corporation)

Location: Ballroom D

Date: Wednesday, January 30

Time: 8:00am - 8:45am

Track: 11. Power Integrity in Power Distribution Networks, 04. System Co-Design: Modeling, Simulation & Measurement Validation

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

This paper presents a new methodology for developing a performance-driven OTN VRM specification. OTN applications have special requirements of maintaining very low noise in low-to-mid frequency range. PLL and transmitter jitter performance is evaluated including three noise sources from device, PDN, and VRM of all power supplies. As an outcome, OTN VRM noise mask is generated by sweeping VRM noise magnitude and frequency for given OTN jitter specification. Example solutions are provided to meet the resultant OTN VRM specifications. The proposed methodology also utilizes a newly-developed accurate on-chip modeling technique which is frequency-dependent and highly distributed.


Transceiver OTN applications are especially sensitive to noise in low-to-mid frequency range. This necessitates new special VRM specifications that facilitate OTN system design. New methodology for performance-driven OTN VRM specifications is developed. New approach to generate the worst-case OTN PDN noise profiles using newly-developed on-chip modeling technique is also discussed.

Intended Audience

Impedance profile, jitter, on-chip modeling and extraction, optical transport network, PDN modeling and simulation, supply noise, VRM

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