Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
Sherman S. Chen (Principle SI/PI engineer, Kandou Bus)
John Phillips (Principal Application Engineer, Cadence Design Systems)
Location: Ballroom C
Date: Thursday, January 30
Time: 9:00am - 9:45am
Track: 02. Chip I/O & Power Modeling & Validation Solutions, 10. Power Integrity in Power Distribution Networks
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Lightning Talks are technical papers that were accepted as part of the DesignCon conference, but are being made available to all attendees as short sessions in the Chiphead Theater.
In this paper, we compared the PDN models obtained with 2.5D extractor and 3D full wave solver. The resulted deviations on both frequency domain impedance curves and time domain power noise brought by these two kinds of models were analyzed. The influences of different 2.5D extractor setting including pin based vs net based, selections of reference nodes, s-parameter vs spice model, are investigated. Similarly, the influences of key 3D solver setup options were also studied and the corresponding effects were summarized. In the end, a set of design guideline on selecting the best approach for different design scenarios are presented.
1. The differences of impedance curve and time domain noise resulted from 2.5D and 3D modelers.
2. The BKM for setting up 2.5D and 3D solver tools.
3. How to select solvers for different design scenarios.