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DesignCon 2019 Presentation Viewer

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Power Integrity Planning & Simulations for a 2048 Processor Compute Card

Jeffrey Smith (CTO, GHz Systems Inc.)

Location: Ballroom G

Date: Thursday, January 31

Time: 9:00am - 9:45am

Track: 11. Power Integrity in Power Distribution Networks

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Power Integrity in Advanced AI compute chassis requires significant planning; With chassis power supplying 8 KO compute cards, 4 ATX processors a chassis can draw ~5.4KW at peak load. Each KO compute card contains 2048 64-bit processor cores in eight Knureon ASIC's and a Xilinx UltraScale FPGA. The FPGA and each Knureon ASIC required local power sequencing, sensing and monitoring of multiple levels of power distribution.

To meet data center safety standards like ISO/IEC 24764 we chose pre-qualified power modules. This configuration could work with a total of 64 chassis configuration of our AI compute server center.

Takeaway

Power Integrity in Advanced AI Compute Nodes requires significant planning; the KO card contains 2048 64-bit processor cores in eight Knureon ASIC's and a Xilinx UltraScale FPGA routing control center. The FPGA and each Knureon ASIC required local power sequencing, sensing and monitoring of multiple levels of power distribution.