DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

DesignCon 2020 Schedule Builder


Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Sign In Create Account Export | Need Help?
All Sessions Speakers My Schedule

Practical Bit Error Rate and RS(544,514) FEC Testing and Troubleshooting for PAM4 Links

Steve Sekel (400G Solutions Specialist, Keysight Technologies)

Charles Seifert (Senior Manager, Product Management, Keysight Technologies)

Location: Great America 1

Date: Thursday, January 30

Time: 10:15am - 10:55am

Track: Keysight Education Forum

Vault Recording: TBD

Optical and electrical links are not expected to have raw, error-free performance. Using PAM4 modulation to reach 400 Gb/s speeds means that engineers must now design, develop, and validate transceivers and network communication devices that have multiple 28 or 56 Gb/s channels. With 4-level signaling and reduced signal-to-noise ratio (SNR), PAM4 links require forward error correction (FEC).